Conventional modeling techniques have been implemented for determining parasitic resistances and capacitances within an electrical circuit layout. However, parasitic inductances between interconnect lines within the circuit have been largely ignored.
As the operational frequencies of electrical circuits increases, inductive coupling between the interconnect lines within a circuit may affect the timing and/or noise analysis of the circuit.
Thus, a need exists for accurately and/or efficiently determining the parasitic inductances within an electrical circuit layout.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn accurately or to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity or several physical components included in one functional block or element. Further, where considered appropriate, reference numerals may be repeated among the drawings to indicate corresponding or analogous elements. Moreover, some of the blocks depicted in the drawings may be combined into a single function.